1. Field of the Invention
The present invention generally relates to a surface discharge plasma display panel (PDP) and, more particularly, to an apparatus and method for driving a surface discharge PDP which control the slope of an erasing pulse to perform the initialization operation in sub-field periods of driving frames.
2. Description of the Related Art
Generally, a surface discharge plasma display panel (referred to as xe2x80x98display panelxe2x80x99 hereinafter) is a light emitting device which excites a fluorescent material placed inside discharge cells thereof, to thereby display images. It is compact, manufactured through simple fabrication processes and easily realized in a large screen so that it is widely used as a bulletin board of a stock exchange, a display for video conferencing and a wide-screen wall-hanged TV.
FIG. 1 roughly illustrates a general circuit for driving the surface discharge PDP. In FIG. 1, reference numeral 10 represents a color three-electrode surface discharge PDP with resolution LxK constructed in a manner that first L sustain electrodes X1xcx9cXL and second L sustain electrodes Y1xcx9cYL are alternately arranged in parallel with each other, K address electrodes A1xcx9cAK intersect the first and second sustain electrodes X1xcx9cXL and Y1xcx9cYL, having predetermined spaces therebetween, and cells S are formed at intersections where the first and second L sustain electrodes X1xcx9cXL and Y1xcx9cYL intersect the K address electrodes A1xcx9cAK, to construct the entire screen of LxK R (red), G (green) and B (blue) cells in a matrix form. Here, the first L sustain electrodes X1xcx9cXL are connected in parallel by a first common sustain electrode.
Reference number 20 in FIG. 1 denotes an X-electrode driver connected to the first sustain electrodes X1xcx9cXL of the panel 10 to provide a driving pulse to them, and 30 represents an Y-electrode driver connected to the second sustain electrodes Y1xcx9cYL, of the panel 10 to supply a driving pulse to them. In addition, reference numeral 40 represents an address driver connected to the address electrodes A1xcx9cAK of the panel 10 to selectively apply a driving pulse to them based on a digital video signal corresponding to each cell S. Reference numeral 50 denotes a system controller which digitalizes an analog video signal IMAGE supplied from the outside to output a digital video signal, and provides various control signals to the X-electrode driver 20, Y electrode driver 30 and address driver on the basis of the digital video signal and various external signals (clock (CLK), horizontal synchronous signal (HS) and vertical synchronous signal (VS)).
FIG. 2 is a cross-sectional view of the cell S in FIG. 1. Referring to FIG. 2, an upper glass 11 and a lower glass 14 placed opposite to the upper glass 11 having a predetermined distance therebetween are combined with each other to construct a predetermined discharge space, that is, the discharge cell. The upper glass 11 is constructed in a manner that a first sustain electrode X and a second sustain electrode Y are formed thereon in parallel with each other, a dielectric layer 12 that restricts discharge current when discharge occurs and facilitates generation of wall charges is formed on the first and second sustain electrodes X and Y, and a MgO protection layer 13 for protecting the first and second sustain electrodes X and Y and the dielectric layer 12 from sputtering during discharge is formed on the dielectric layer 12. The lower glass 14 is constructed in such a manner that an address electrode A is formed on the plane opposite to the upper glass 11, first and second barriers 15a and 15b for preventing color mixture between cells and securing the discharge space are formed at both sides of the address electrode A in parallel therewith, and a fluorescent material 16 is coated on the address electrode A and parts of the first and second barriers.
The basic operation of the cell constructed as above is explained below with reference to FIGS. 3 and 4.
In the display panel, generally, the span of time for displaying one image is divided into a plurality of frames F1xcx9cFn as shown in FIG. 3(A), each frame F being split into a plurality of sub-fields SF1xcx9cSFM as shown in FIG. 3(B). In case of realization of 256 gray scales, for instance, one frame F is constructed of eight sub-fields SF1xcx9cSF8 to provide signals of the display panel. Each sub-field SF includes an initialization period, a data addressing period and a sustaining period, as shown in FIG. 3(C), to be provided with a predetermined signal.
That is, the sub-field SF applies a voltage with a predetermined level, 70V, for example, to the address electrode A first, and supplies the high voltage writing pulse of 400V, for example, to the first sustain electrode X during a period (a), as shown in FIG. 4. Here, cells S which were written or not written in the previous sub-field perform discharge according to the high voltage. At this time, excessive wall charges in the cells S formed by the high voltage generate self-erase discharge due to inner wall charges after falling of a writing pulse. Accordingly, negative wall charges are created in the first sustain electrode X and positive wall charges are formed in the second sustain electrode Y.
Subsequently, a predetermined erasing pulse is applied to the second sustain electrode Y while voltages of the address electrode A and the first sustain electrode X being set to a predetermined level, 0V, during periods (b) and (c). This erases the wall charges formed in the second sustain electrode Y during the period (a). That is, a small amount of negative wall charges formed in the first sustain electrode X and a small quantity of positive wall charges created in the second sustain electrode Y are neutralized in the discharge space according to the erasing pulse applied to the second sustain electrode Y, to thereby remove the wall charges remaining in the cell S.
Through the aforementioned initialization operation, electron and wall charge components formed in the first and second sustain electrodes X and Y of the cell S are cleared, and then 70V, for example, is applied to the address electrode A, 50V, for example, is applied to the first sustain electrode X, and a reverse voltage (negative voltage) with a predetermined level is applied to the second sustain electrode Y, to perform data addressing operation through the address electrode A. Here, discharge for data addressing occurs in the address electrode, first and second sustain electrodes X and Y. At this time, discharge of the first and second sustain electrodes X and Y is facilitated according to charged particles in the discharge space so that generation of secondary discharge forms negative wall charges in the first sustain electrode X and positive wall charges in the second sustain electrode Y, during a period (d).
Subsequently, the voltages of the address electrode A, first and second sustain electrodes X and Y are set to 0V, for instance, at a point of time when the data addressing period of the sub-field SF is finished, and a predetermined positive voltage is applied to the second sustain electrode Y, to generate discharge caused by the positive wall charges in the cell S, created in the second sustain electrode Y during the data addressing period (d) and the voltage applied from the outside in the first electrode X during a period (e). That is, a predetermined sustaining pulse is applied to the second sustain electrode Y.
After supply of the sustaining pulse to the second sustain electrode Y, as described above, a predetermined positive voltage is provided to the first sustain electrode X to discharge the positive wall charges formed in the first sustain electrode X to the second sustain electrode Y. In other words, a predetermined sustaining pulse is applied to the first sustain electrode X during a period (f).
Thereafter, the operations (e) and (f) are alternately performed during the sustaining period of the sub-field SF to finish one sub-field operation. The operation of the sub-field, as described above, is repeated.
However, the initialization operation, constructed in a manner that the high voltage of +400V, that is, a writing pulse, is applied to the first sustain electrode X in the sub field SF and then a predetermined erasing pulse is provided to the second sustain electrode Y to erase positive charges formed in the first or second sustain electrode X or Y, that are caused by application of the last sustaining pulse to the sustain electrode during the last sustaining period of the previous sub-field, results in supply of the high voltage Nxc3x97M times in case where N frames construct one picture and one frame F consists of M sub-fields SF.
Furthermore, the multi-time supply of the high voltage decreases reliability of the circuit for driving the PDP and increases power consumption.
Moreover, the repeated supply of the high voltage shows picture characteristic having brightness of 4 cd approximately when a black picture is expressed, deteriorating the contrast of the display panel.
It is, therefore, an object of the present invention to provide an apparatus and a method for driving a PDP, which adjust the slope of an erasing pulse to erase charges remaining in the previous sub-field during the initialization period of sub-fields constructing one frame and provide a high voltage writing pulse in at least one frame, to thereby minimize consumption power due to the writing pulse and deterioration of the contrast picture characteristic.
To accomplish the object of the present invention, there is provided an apparatus for driving a surface discharge plasma display panel including a panel constructed of M first and second electrodes and K address electrodes, and a system controller for controlling driving power supplied to the first and second electrodes and the address electrodes, the plasma display panel being constructed in a manner that a frame for displaying an image is divided into N sub-fields, each sub-field is composed of an erasing period, an addressing period and a sustaining period, and the second electrodes have an erasing pulse generating means providing an erasing pulse during the erasing period, wherein the system controller comprises a counter for counting the number of sustaining pulses applied to the first electrode by sub-fields, a data memory for storing erasing pulse slope information corresponding to the number of the sustaining pulses, and a signal processor for reading corresponding slope information from the data memory and transmitting read slope information to the erasing pulse generating means based on the information about the number of sustaining pulses supplied from the counter, and the pulse generating means generates an erasing pulse having a slope based on the slope information supplied from the signal processor, the slope corresponding to the slope information.
To accomplish the object of the present invention, there is also provided a method for driving a surface discharge plasma display panel in which a driving voltage supply frame for displaying an image is constructed of N sub-fields, and each sub-field is composed of an erasing period, an addressing period and a sustaining period, the sustaining period alternately providing a predetermined sustaining pulse to first and second electrodes constructing the display panel, the method comprising: a sustaining pulse counting step for counting the number of sustaining pulses by sub-fields, which are generated in the first electrode to which the final sustaining pulse of the sub-fields is supplied during the sustaining period of each sub-fields; and an erasing pulse supplying step for providing an erasing pulse having a slope to the second electrode on the basis of erasing pulse slope information corresponding to information about the number of the sustaining pulses counted in the sustaining pulse counting step, the slope of the erasing pulse corresponding to the erasing pulse slope information.
Furthermore, the apparatus and method for driving a surface discharge PDP according to the present invention apply a high voltage writing pulse to the first sustain electrode when a sub-field period corresponding to at least one frame has been finished.
According to the present invention, the slope of the erasing pulse is controlled to correspond to remaining charges generated by supplying the sustaining pulse, to improve the picture quality of black pictures due to the high voltage and reduce the number of times of providing the high voltage writing pulse, resulting in the realization of a PDP with low consumption power.